The present disclosure relates in general to a voltage detection circuit. In particular, the present disclosure relates to a voltage detection circuit for power-on detection with temperature compensation.
FIG. 1 shows a circuit diagram of a conventional power-on detection circuit. The power-on detection circuit 100 comprises a voltage detection circuit 110 and a RC-filter 120.
The voltage detection circuit 110 comprises a PMOS transistor MP1, NMOS transistors MN1, MN2, and a resistor R1. The NMOS transistor MN1 and PMOS MP1 transistor comprise a voltage reference circuit. The drain and gate of the PMOS transistor MP1 are both coupled to node A, to which the drain and gate of the NMOS transistor MN1 are both coupled. The node A is coupled to the gate of the NMOS transistor MN2. Resistor R1 is coupled between the drain of the NMOS transistor MN2 and the voltage source VCC.
The PMOS transistors MP1 and the NMOS transistor MN1 from a voltage divider to generate a reference voltage at node A. The reference voltage is determined by threshold voltages Vthn1 and Vthp1 of the NMOS transistor MN1 and of the PMOS transistor MP1 respectively. The NMOS transistor MN2 is configured as a common-source with a passive load R1 for outputting the detecting result at node B.
At power-on, voltage source VCC is increased from 0V. Thus, the voltage level of node A is lower than the threshold voltage Vthn2 of NMOS transistor MN2. Therefore, NMOS transistor MN2 is turned off, NMOS transistor MN3 is turned on, and output terminal OUT of inverter 130 is low. When voltage source VCC reaches a predetermined value causing the voltage level of node A exceed the threshold voltage Vthn2 of NMOS transistor MN2, NMOS transistor MN2 is turned on and NMOS transistor MN3 is turned off. Thus, output terminal OUT of inverter 130 is at high voltage after a RC delay period.
When the process or temperature induce variations in the threshold voltage Vthn2 of the NMOS transistor MN2, the threshold voltage Vthn1 of the NMOS transistor MN1 varies correspondingly. Thus, the reference voltage corresponds to the threshold voltage Vthn1 of the NMOS transistor MN1. When the voltage VCC remains the same, the variation of the reference voltage compensates for the variation in the threshold voltage Vthn2 of the NMOS transistor MN2. Therefore, the voltage of node B remains constant without suffering from the variation of the threshold voltage Vthn.
However, the voltage detection of the power-on detection circuit 100 is imprecise when the voltage source VCC is scaled down by the advance process. Due to the variation of threshold voltages Vthn1, Vthn2 and Vthp not scaled down with process, variations of the detected voltage are very large and voltage overhead may result.
FIG. 2 shows another conventional power-on detection circuit. The power-on detection circuit comprises a voltage detection circuit 20 and a RC-filter 22. The gate of NMOS transistor M11 is connected to its drain. The gate of NMOS transistor M12 is connected to its drain at node B. The sources of NMOS transistors M11 and M12 are connected to ground. In addition, the aspect ratio of the NMOS transistor MN11 is N times larger than that of the NMOS transistor MN12. Thus, N numbers of NMOS transistors connected in parallel comprise the NMOS transistor MN11.
Comparator 201 comprises a first input terminal connected to node A, a second input terminal connected to node B, and output terminal VOUT. The voltage level of node A is voltage VA, and that of node B is voltage VB. Comparator outputs low voltage when voltage VA is lower than voltage VB, and outputs high voltage when voltage VA exceeds voltage VB.
Resistor R0 is connected between node A and the gate and drain of the NMOS transistor M11. Resistor R13 is connected to the power source VCC. Resistor R11 is connected between node A and resistor R13. Resistor R12 is connected between node B and resistor R13.
During the power-on process, the voltage source VCC is initially increased from 0V, before reaching a predetermined voltage level Vrr, voltage VA is lower than the voltage VB, and the output terminal VOUT of the comparator 201 is at low level. Until the voltage source VCC rises to the predetermined voltage level Vrr, the output terminal VOUT of the comparator 201 is at high level margin.
When the voltage source VCC reaches the predetermined voltage level Vrr, the voltage VA is equal to voltage VB. At this time, comparator 201 detects the voltage VA and VB, and its output terminal VOUT transitions from low level to high level. Subsequently, the voltage VA exceeds the voltage VB. Thus, the output terminal VOUT of the comparator 201 is at high level margin. Thus, NMOS transistor M13 is turned on by the comparator 201, and output terminal OUT is at a high voltage after a RC delay period.
Equation (1) describes the drain current ID of a MOS transistor.                                                                         I                D                            ⁢                            =                                                μ                  n                                ⁢                                  C                                      d                    ⁢                                                                                                                ⁢                                  W                  L                                ⁢                                                                            V                      T                      2                                        ⁡                                          (                                              exp                        ⁢                                                                                                            V                              GS                                                        -                                                          V                              TH                                                                                                            ζ                            ⁢                                                                                                                  ⁢                                                          V                              T                                                                                                                          )                                                        ·                                      (                                          1                      -                                              exp                        ⁢                                                                              -                                                          V                              DS                                                                                                            V                            T                                                                                                                )                                                                                                                                        ⁢                              ≅                                                      μ                    n                                    ⁢                                      C                    d                                    ⁢                                      W                    L                                    ⁢                                                            V                      T                      2                                        ⁡                                          (                                              exp                        ⁢                                                                                                  ⁢                                                                                                            V                              GS                                                        -                                                          V                              TH                                                                                                            ζ                            ⁢                                                                                                                  ⁢                                                          V                              T                                                                                                                          )                                                                                                                                                            ⁢                              =                                  A                  ⁢                                                                          ⁢                                      μ                    n                                    ⁢                                                            V                      T                      2                                        ⁡                                          (                                              exp                        ⁢                                                                                                            V                              GS                                                        -                                                          V                              TH                                                                                                            ζ                            ⁢                                                                                                                  ⁢                                                          V                              T                                                                                                                          )                                                                                                                              (        1        )            where             V      T        ≡          KT      q        ;      ζ    ≡          1      +                        C          d                          C          OX                      ;      A    ∝          W      L      
Let VGS−VTH=VOV, thus:VOV=ζVT[ln(ID)−ln(AμnVT2)]  (2)
According equation (2), VGS1 and VGS2 respectively of NMOS transistors M11 and M22 are:
VGS1=VOV1+VTH=ζVT[ln(ID1)−ln(AμnVT2)]+VTH  (3)                                                                        V                GS2                            =                                                V                  OV2                                +                                  V                  TH                                                                                                        =                                                ζ                  ⁢                                                                          ⁢                                                            V                      T                                        ⁡                                          [                                                                        ln                          ⁡                                                      (                                                                                          I                                D1                                                            ·                              m                              ·                                                              R11                                R12                                                                                      )                                                                          -                                                  ln                          ⁡                                                      (                                                          A                              ⁢                                                                                                                          ⁢                                                              μ                                n                                                            ⁢                                                              V                                T                                2                                                                                      )                                                                                              ]                                                                      +                                  V                  TH                                                                                        (        4        )            
As mentioned, the voltage VA is equal to voltage VB when the voltage source VCC reaches the predetermined voltage level Vrr. Thus, the voltage difference ΔVOV across resistor R0 is:                                           V            GS1                    -                      V            GS2                          =                                            V              OV1                        -                          V              OV2                                =                                    Δ              ⁢                                                          ⁢                              V                OV                                      =                          ζ              ⁢                                                          ⁢                              V                T                            ⁢                              ln                ⁡                                  (                                      m                    ·                                          R11                      R12                                                        )                                                                                        (        5        )            
Thus, the voltage difference ΔVOV is increased incrementally as temperature increases. In addition, NMOS transistors M11 and M12 are biased in the sub-threshold region, such that the threshold voltage VTH NMOS transistors M11 and M12 are decreased incrementally as temperature increases, which are the voltage difference between the drain and the source of the NMOS transistors M11 and that of NMOS transistors M12 respectively.
When the voltage VCC remains at Vrr and the variation of temperature, the variation of voltage difference ΔVOV compensates for the variation of the voltage difference between the drain and the source of the NMOS transistors M11 and M12.
In addition, when the voltage VA is equal to voltage VB, the voltage level Vrr is:                                                                         V                rr                            =                            ⁢                                                V                  OV1                                +                                  V                  TH                                +                                                      (                                                                  Δ                        ⁢                                                                                                  ⁢                                                  V                          OV                                                                    R0                                        )                                    ⁢                                      (                                          R11                      +                      R0                                        )                                                  +                                                                                                      ⁢                                                (                                                            Δ                      ⁢                                                                                          ⁢                                              V                        OV                                                              R0                                    )                                ⁢                                  (                                      1                    +                                          R12                      R11                                                        )                                ⁢                R13                                                                                        =                            ⁢                                                V                  OV1                                +                                                                            V                      TH                                        ⁡                                          (                                                                        Δ                          ⁢                                                                                                          ⁢                                                      V                            OV                                                                          R0                                            )                                                        ⁡                                      [                                                                  (                                                  R11                          +                          R0                                                )                                            +                                                                        (                                                      1                            +                                                          R12                              R11                                                                                )                                                ⁢                        R13                                                              ]                                                                                                          (        6        )            
According to equations (1) and (5), the voltage difference ΔVOV and current ID1 and ID2 are increased incrementally as temperature increases. In addition, VOV1 is increased with the increased current ID1. Thus, the first term (VOV1) and third term of equation (6) have a positive temperature coefficient (PTC), and the second term (VTH) of equation (6) has a negative temperature coefficient (NTC) and a fixed factor. Thus, a adjustable voltage level Vrr with temperature compensation is unable obtained.